The present invention relates to integrated circuits, and more particularly, to a voltage-switching device of the type using a high-voltage translator.
Voltage-switching devices are used especially in non-volatile memory integrated circuits to apply the appropriate voltage levels to the memory cells as a function of the operation to be performed. In these applications, different levels of low voltage and high voltage are applied to perform various read and write (programming, erasure) operations.
In integrated circuits using low voltage technologies, the electronic elements cannot withstand excessively high voltages. In particular, the oxides are highly vulnerable. In a practical example, with transistors having double oxide thicknesses, these transistors cannot withstand more than five volts of a gate-source voltage, a gate-drain voltage or a source-drain voltage. Especially in non-volatile memory applications, high voltages are applied for write operations, and the oxides of certain transistors are subjected to voltages far above five volts.
As illustrated schematically in FIG. 1, memories are commonly organized in matrix form, in bit lines B1 and word lines W1. Each bit line B1 connects the drains of the memory cells in one column and each word line W1 connects the gates of the memory cells in one row.
There are various architectures in existence. In particular, the bit lines may be grouped by databanks DATABANK0-DATABANKn enabling simultaneous access to several memory cells in one databank located on the same row. In these architectures, the selection of a memory address comprises the selection of a corresponding word row or line and of the bit lines of the corresponding bank.
This address selection is carried out by decoding circuits. These decoding circuits are used for the selection of the memory cells or cells corresponding to a memory address presented at input, by applying appropriate voltage levels to these cells as a function of the requested operation. As illustrated in FIG. 1, there is a column address decoding circuit DECY and a row address decoding circuit DECX.
The invention relates more particularly to the column address decoding circuits DECY. The row decoding circuit DECX outputs low-voltage or high-voltage levels for each row. These levels are directly applied to the gates of the cells of the memory. The row-decoding circuit has a translator type circuit having an adapted structure, especially a cascode-stage structure, to provide the desired voltage levels.
However, the column-decoding circuit, for its part, gives a low-voltage (0, Vdd) or a high-voltage (0, HV) logic control signal that is applied to one or more switching transistors of a multiplexer circuit MUXY which connects the I/O read/write circuits to the bit lines B1 of the memory. In programming (or erasure), a switching transistor may have a high-voltage applied to its drain (or source) by the write circuits, while its gate has a high-voltage logic signal applied to it. This signal may be either at 0 or at the high-voltage level. In one case, the switching transistor is off. In the other case, it is on and its drain (or source) level is transmitted to a bit line of the memory.
In an integrated circuit made in low-voltage technology, these switching transistors are particularly vulnerable. The column address decoding circuit DECY comprises a decoding circuit that gives low-voltage (0, Vdd) logic address selection signals Com-topi as a function of the column address ADRY that is applied to it, and a memory control signal READ whose level 0 or 1 indicates a write or read operation.
Each address selection signal Com-top is applied to a high-voltage translator type circuit HV-Switch, whose output Yocti is used to control one or more gates of the multiplexer circuit MUXY placed between the bit lines B1 of the memory and the read/write I/O circuits. Each output signal Yocti has a voltage level that depends on the associated selected signal Com-topi, and on the operation to be performed in the memory, namely on the memory control signal READ.
The multiplexer circuit MUXY is usually based on a gate structure enabling the connection of a read or write circuit to a selected bit line of the memory. Each gate is controlled by one of the signals Yocti given by the column address decoding circuit. In the exemplary structure shown in FIG. 1, the multiplexer MUXY has one set of gates per group of bit lines G0-Gn corresponding to a databank DATABANK0-DATABANKn. Each set of gates is controlled by a corresponding selection signal Yocti. In this example, there is one output signal Yocti per set of gates of the multiplexer, namely per databank of the memory.
The number of gates controlled by one output selection signal Yocti, as well as the number of gates to control a bit line, depend on the memory architecture and the number of decoding levels of the address decoding circuit. FIG. 1 shows one possible structure among others. In the prior art, the gates of the multiplexer are usually NMOS transistors. For a read operation, these are low-voltage logic signals. They typically take the level of ground 0V in the case of non-selection (with NMOS transistor off), and the level of the logic supply voltage Vdd (or a lower level), for example 2.5 volts, in the case of selection (with NMOS transistor on).
For a write operation, these are high-voltage logic signals. They typically take the level of ground 0V in the case of non-selection (with the NMOS transistor off), and a high-voltage level, for example 12 volts, in the case of selection (with the NMOS transistor on) enabling a high-voltage level in the range of 7.5 volts to be made to go from its drain to its source. In integrated circuits using low-voltage technology, it has been noted that these switching transistors are fragile because of the voltage levels that may be applied to them in the writing mode. For these reasons, other gate structures that are more stress-resistant are used.
The invention is concerned with a data structure using complementary MOS transistors in which the NMOS transistor is the active transistor in read mode, and the PMOS transistor is the active transistor in write mode. These transistors then receive a complementary control signal at their gates.
The PMOS transistor has the advantage over the NMOS transistor of switching the high-voltage without losses. To turn it off, the high-voltage must be applied to its gate. To turn it on, and switch the high-voltage applied to its source to its drain without losses, it is enough to apply a voltage level to it that is lower than a little more than a transistor threshold with respect to the high-voltage.
In the invention, it is proposed, in write mode, to apply the voltage level Vdd instead of the 0 voltage level to the gate of the PMOS transistor, or in general, a low-voltage logic level such that the difference between the high-voltage level and the level applied to the gate remains smaller than or equal to the borderline voltage acceptable across the oxide.
Thus, by using the low-voltage high logic level, Vdd in the example, a desired control is achieved over the PMOS transistor, and this is achieved without stress. The parallel-connected NMOS transistor, controlled at its gate by a signal complementary to that of the PMOS transistor, experiences equivalent voltage levels. This transistor is also without stress.
This problem of controlling high-voltage switching transistors may also occur, depending on the architecture, in the write circuits, for application of the high-voltage upline from the multiplexer (assuming that the bit lines are downline) as a function of the data element 0 or 1 applied to the input of the write circuits to switch the high-voltage level Vpp=HV or the low-voltage logic level Vdd to the source of the PMOS transistor. Thus, a general problem of the invention pertains to the control of switching MOS transistors in integrated circuits made in low-voltage technology.
In the exemplary generation of appropriate voltage levels for the control Yoct of the gate of a PMOS transistor that is active in write mode and /Yoct for the control of an NMOS transistor that is active in read mode, assuming by convention that the signal Com-top is active at 0 (selection of the associated bit line or lines), the high-voltage switching device provides the following levels as illustrated in Table 1.
There is a translation of the logic levels between the read mode and the write mode. The control of the multiplexer in write mode becomes an analog type of control. The high-voltage translator circuits of the prior art cannot be used to give a gate control signal of this type. At an output, the circuits can give only 0 and Vpp=Vdd in read mode and Vpp=HV in write mode.
An object of the present invention is to provide a device that generates voltage levels suitable for low-voltage technologies, particularly for non-volatile memory applications.
A control signal is provided with shifted or analog voltage levels as a function of a given control signal. The invention is not limited to the exemplary application given. It can be applied more generally to any circuit requiring analog voltage levels.
The invention therefore relates to a voltage-switching device comprising a high-voltage translator connected to a high-voltage node receiving either a low-voltage logic level or a high-voltage level as a function of a low voltage/high-voltage mode control signal. The translator provides at least one output signal as a function of this mode control signal and of a switching control signal.
The voltage-switching device further comprises a voltage-level switching circuit. This circuit is controlled by output signals of the high-voltage translator and by the mode and switching control signals for the application, as output voltage levels, of either ground or the low-voltage logic level in low-voltage mode or the low-voltage logic level or the high-voltage level in high-voltage mode.
The invention also relates to an integrated circuit comprising a switching device of this kind, especially an integrated circuit with non-volatile memory.